Synective CAN/CAN FD IP
Delivered as a netlist with full documentation and sample code for integration
The IP can optionally be delivered with full source code
Available for most Xilinx, Altera, Lattice and Microsemi devices
Proven in products that are in production as well as in ASICs
For more details, see the one pager here
The Synective CAN 2.0 and CAN FD IP core implements a complete CAN controller for integration into FPGAs and ASICs. The IP is compliant to the new ISO 11898-1:2015 standard, supporting both standard CAN and CAN FD. CAN FD is a new version of the CAN standard, where the payload is sent at a higher bitrate (up to 10 Mbit/s). The payload can also be up to 64 bytes long, compared to 8 bytes for normal CAN.
The IP is targeted at high-end systems and allows high efficiency with FIFO buffers at transmitter and receiver end. The transmit packet acknowledge data stream with tag information allows efficient transmission buffer management. The dual-destination buffer DMA functionality is designed for minimal added latency and an interrupt frequency that scales down as needed at higher system loads.
The IP is available for most Xilinx, Altera, Lattice and Microsemi FPGA devices, supporting native bus interfaces like AXI and Avalon. Processor integration is available for SOC type of FPGAs.
The IP is designed with many features for diagnosis and CAN bus debugging, making it ideal for data loggers and similar devices. All these features can be disabled at build time, to minimize footprint for more traditional applications.
The IP can be configured with multiple channels with a shared receive buffer and individual transmit buffers, potentially saving precious resources.
It is also possible to directly interface the BSP (Bit Stream Processor) block. This is the core module of the IP, stripped of buffers and many features, thus making it very small. Approximate resource usage is 1,100 4-input LUTs and 330 registers.
The IP is verified against the Bosch reference model for the ISO 11898-1:2015 standard and is 100% compliant. It has also been tested extensively by the C&S test institute.
|CAN FD, both ISO and non-ISO||CAN 2.0A and 2.0B|
|Small Footprint||System Bus Interface|
|Multiple Channels||Configurable Hardware Buffer Sizes|
|Status Updates in Data Stream||Interrupt Logic|
|Low-Latency DMA with Interrupt Rate Adaptation||Transmit Rate Adaptation|
|Self-Listen-Mode||Auto Acknowledge Mode|
|Single Shot Mode||Separate System Bus and Core Clocks|